1.Field of the Invention
This invention relates in general to systems that utilize phase synchronized clock signals or similar synchronous signals used in circuit operations, and more particularly to a system that measures phase differences between synchronous signals to a high precision. 2. Description of Related Art
A variety of electronic devices, such as computers, monitors, flat panel displays, wireless communication devices, cellular phones, high speed two-way digital transceivers, and paging devices, to name just a few, utilize a plurality of synchronous signals, e.g., clock signals, vertical-synch and horizontal-synch signals, spread spectrum and digital wireless communication signals, etc., that are phase synchronized with other signals associated with such devices. A key part of the synchronization function is usually handled by a phase-locked loop circuit. A phase comparator or phase detector constitutes a main functional component in the signal phase synchronization process.
Phase detectors have been conventionally manufactured using all analog circuit construction. An analog phase detector produces an analog output signal, for example a voltage signal, to indicate a phase difference. In a phase-locked loop, for example, this analog signal may control a frequency source, such as a voltage controlled oscillator (VCO). High precision adjustments in the frequency signal output from the VCO may depend on very precise, custom analog circuit design and components for an analog phase detector.
Analog phase lock loops, as with most analog circuit designs, suffer from sensitivity to noise signals, temperature variability, and manufacturing process variations. Further, to increase the precision of an analog circuit may require significant additional component cost and multiple fabrication iterations. Furthermore, analog circuit designs tend to require large circuit real estate such as to implement a precision phase lock loop circuit. Additionally, as with any analog circuit design, the design time tends to be long in order to port a design to a new circuit manufacturing process. To transfer an analog phase lock loop to a new manufacturing process, the design effort and risk are substantially the same as the original design.
With the increasing popularity of digital circuits in all of the aforementioned devices, the trends are 1) toward smaller and more compact devices requiring smaller real estate circuit designs, 2) continuous improvements in circuit manufacturing technologies requiring easily adaptable circuit designs for new technologies, and 3) increasing demand for higher precision signal phase synchronization. It is unfortunate, therefore, that there is not available a high precision all digital phase comparator circuit for such electronic devices and that overcomes the disadvantages of the prior art as discussed above.
Thus, there is a need to overcome the disadvantages of the prior art as discussed above.
Briefly, in accordance with a preferred embodiment of the present invention, a system for high precision measurement of a phase difference between two signals comprises: a first input for receiving a first signal with a first edge; a second input for receiving a second signal with a second edge; a first delay chain comprising a first at least one delay element, the first delay chain electrically coupled to the first input such that the first signal is delayed across the first at least one delay element, each of the first at least one delay element comprising an output tap; a second delay chain comprising a second at least one delay element, the second delay chain electrically coupled to the second input such that the second signal is delayed across the second at least one delay element, each of the second at least one delay element comprising an output tap; and at least one set of symmetrical combinational logic gates arranged as a symmetrical Flip-Flop, each of the at least one Flip-Flop including a first and second input electrically coupled to an output tap of each of the first and second at least one delay element, respectively, such that an output of each of the at least one Flip-Flop indicates which of the first edge of the first signal from the output tap of one of the first at least one delay element and the second edge of the second signal from the output tap of one of the second at least one delay element arrived first at the respective first and second input of the at least one Flip-Flop.
Additionally, according to a preferred embodiment of the present invention, a flat panel monitor comprises: a controller for controlling functions of the flat panel monitor; a display for displaying information; a video interface Including a first input for receiving a first signal with a first edge; and a digital PLL, electrically coupled to the video interface, the controller, and the display, for generating, at a second input, a second signal with a second edge, the digital PLL including: a first delay chain comprising a first at least one delay element, the first delay chain electrically coupled to the first input such that the first signal is delayed across the first at least one delay element, each of the first at least one delay element comprising an output tap; a second delay chain comprising a second at least one delay element, the second delay chain electrically coupled to the second input such that the second signal is delayed across the second at least one delay element, each of the second at least one delay element comprising an output tap; and at least one set of symmetrical combinational logic gates arranged as a symmetrical Flip-Flop, each of the at least one Flip-Flop including a first and second input electrically coupled to an output tap of each of the first and second at least one delay element, respectively, such that an output of each of the at least one Flip-Flop indicates which of the first edge of the first signal from the output tap of one of the first at least one delay element and the second edge of the second signal from the output tap of one of the second at least one delay element arrived first at the respective first and second input of the at least one Flip-Flop.
Furthermore, according to a preferred embodiment of the present invention, an integrated circuit comprises: a first input for receiving a first signal with a first edge; a second input for receiving a second signal with a second edge; a first delay chain comprising a first at least one delay element, the first delay chain electrically coupled to the first input such that the first signal is delayed across the first at least one delay element, each of the first at least one delay element comprising an output tap; a second delay chain comprising a second at least one delay element, the second delay chain electrically coupled to the second input such that the second signal is delayed across the second at least one delay element, each of the second at least one delay element comprising an output tap; and at least one set of symmetrical combinational logic gates arranged as a symmetrical Flip-Flop, each of the at least one Flip-Flop including a first and second input electrically coupled to an output tap of each of the first and second at least one delay element, respectively, such that an output of each of the at least one Flip-Flop indicates which of the first edge of the first signal from the output tap of one of the first at least one delay element and the second edge of the second signal from the output tap of one of the second at least one delay element arrived first at the respective first and second input of the at least one Flip-Flop. dr
FIG. 1 is a block diagram illustrating an exemplary electronic device, such as a flat panel monitor display device, in accordance with a preferred embodiment of the present invention.
FIG. 2 is a circuit block diagram of the exemplary electronic device of FIG. 1 comprising a digital phase lock loop (PLL) implementation utilizing a high precision digital phase comparator, in accordance with a preferred embodiment of the present invention.
FIGS. 3 and 4 are more detailed circuit block diagrams of the phase comparator shown in FIG. 2, according to a preferred embodiment of the present invention.
FIG. 5 is a more detailed circuit block diagram of the digital DLL and controller shown in FIG. 2, in accordance with a preferred embodiment of the present invention.
FIG. 6 is a more detailed circuit block diagram of a digitally programmable delay element in the programmable delay chain shown in FIG. 2, in accordance with a preferred embodiment of the present invention.
FIG. 7 is a more detailed circuit block diagram of a Non-glitching MUX shown in FIG. 2, according to a preferred embodiment of the present invention.
FIG. 8 is a more detailed circuit block diagram of a system controller and loop filter illustrated in FIG. 2, in accordance with a preferred embodiment of the present invention.